Senior Layout Engineer

Sr. Layout Engineer (High-Speed)
Requirements for Analog & Mixed Signal Layout:
Chip floor planning, device placement, routing, verifications, layout/design reviews.
Be able to provide the estimated tape-out schedule, plan and execute to meet project milestone deadlines.
Should be familiar with all Layout verification (DRC/LVS/ANT/ESD, etc…) and be able to solve/debug issues independently.
Able to communicate & work with overseas' team to deliver high quality layout that meets design requirements.
Deep understanding of FinFET process and matching requirements.
Understanding of routing and parasitic matching of high-speed routes.
Understanding of hierarchical planning and integration, chip design from block-level to top-level for high-speed mixed signal ICs.
Strong knowledge of device matching, signal shielding & isolation techniques.
Work independently & be able to collaborate with Design, CAD, Technology Development & Package team.
Successfully develop & responsible for the full chip from feasibility to tape-out.
Qualifications:
7+ years of experience with strong full-custom Analog / Mixed Signal layout skills.
Experience with Cadence LVS/DRC tools (QRC, Star RC, Calibre), Cadence Virtuoso XL (VXL) tools.
Data management tools in a Unix environment.
Effective communication & written skills are a must.
A good team player & a quick learner.
Please send me your updated CV if you are interested in this.

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