.Please note that candidates must have the right to live and work in the respective European country before applying. Visa sponsorship will only be considered for exceptional senior engineers with relevant industry experience for positions based in Barcelona, Spain. We are seeking a highly skilled Principal Digital Design Engineer with a proven track record in digital design and verification/infrastructure development for digital FPGAs/ASICs. This role demands expertise in technical and project leadership within digital teams, encompassing documentation, RTL design, and familiarity with backend flow and tools. The position requires strong technical acumen and leadership capabilities to oversee the development and technical/schedule management of PMICs. The ideal candidate will collaborate closely with multidisciplinary groups to drive the design of ASICs and power management ICs aligned with product requirements. Key Responsibilities Lead the design and support verification of digital architectures and functional blocks at the chip level. Produce comprehensive technical documentation including specifications, block diagrams, and requirements for stakeholders. Collaborate across departments and with stakeholders to define architectures, requirements, and resolve design, application, or test issues involving Digital/Analog Design, Application/Test Engineering, and Reliability/Operations. Develop system and chip level simulation verification techniques and methodologies. Execute Digital Design (RTL design) from concept to implementation for ASIC or FPGA. Guide the development of test plans, test benches, and automated test cases for Digital Verification. Manage synthesis, timing closure, and formal verification activities. Develop scripts to automate design and verification processes. Estimate and manage tasks and timelines to meet project schedules. Qualifications PhD/BS/MS in Electrical Engineering with a focus on Digital Design/VLSI coursework. Over 10 years of experience in ASIC or FPGA design and verification. Expertise in power management DC-DC converters and control topologies such as PWM control, constant-on-time control, and voltage/current mode controls. Proficiency in DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, coverage metrics reporting/tracking. Strong programming, scripting, and automation skills (C/C++, shell, Perl, TCL, Python, etc.). Thorough understanding of the ASIC Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc. Experience with industry-standard ASIC tools and flows (Digital Simulators, synthesis tools, DFT, LEC, STA, etc.). Excellent written and verbal communication skills with a collaborative team spirit. Desired experience with automotive standards/FuSA, I2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN, Embedded MCU (ARM/RISC V) designs, and SoC development
