Inria, the French national research institute for the digital sciences
Organisation/Company: Inria, the French national research institute for the digital sciences
Research Field: Computer science
Researcher Profile: First Stage Researcher (R1)
Country: France
Application Deadline: 23 Dec 2024 - 23:00 (UTC)
Type of Contract: Temporary
Job Status: Full-time
Hours Per Week: 38.5
Offer Starting Date: 1 Oct 2024
Is the job funded through the EU Research Framework Programme? Not funded by a EU programme
Reference Number: 2023-05930
Is the Job related to staff position within a Research Infrastructure? No
Offer Description Context and background: Nowadays, there is a growing and irreversible need to distribute Artificial Intelligence (AI) applications from the cloud to edge devices, where computation is largely or completely performed on distributed Internet of Things (IoT) devices. This trend aims to address issues related to data privacy , bandwidth limitations , power consumption reduction and low latency requirements , especially for real-time, mission- and safety-critical applications (e.g., in autonomous driving, support for gesture and medical diagnosis, smart power grid or preventive maintenance).
The direct consequence is the intense activity in designing custom and embedded Artificial Intelligence HardWare architectures (AI-HW) to support energy-intensive data movement , speed of computation , and large memory resources that AI requires to achieve its full potential. Moreover, explaining AI decisions , referred to as eXplainable AI (XAI) , is highly desirable in order to increase the trust and transparency in AI, safely use AI in the context of critical applications, and further expand AI application areas. Nowadays, XAI has become an area of intense interest.
AI-HW, similar to traditional computing hardware, is subject to faults that can have several sources: variability in fabrication process parameters, latent defects or even environmental stress. One of the overlooked aspects is the role that HW faults can have in AI decisions . Indeed, there is a common belief that AI applications have an intrinsic high-level or resilience w.r.t. errors and noise. However, recent studies in the scientific literature have shown that AI-HW is not always immune to HW errors. This can jeopardize all the effort of having an explainable AI , leading any attempt to explainability to be either inconclusive or misleading . In other words, AI algorithms retain their accuracy and explainability property under the condition that the hardware wherein they are executed is fault-free.
Therefore, before explaining the decision of an AI algorithm - to gain confidence and trust in it - firstly the reliability of the hardware executing the AI algorithm needs to be guaranteed, even in the presence of hardware faults. In this way, trust and transparency of an implemented AI model can be ensured, not only in the context of mission- and safety-critical applications, but also in our everyday life.
The goal of the Ph.D. thesis is to study the impact of hardware faults not only on the AI decisions, but also on algorithms developed to explain AI (XAI) models. The objective is to make AI-HW reliable by understanding how hardware faults (due to variability, aging, external perturbations) can impact AI and XAI decisions and how to mitigate those impacts efficiently. The final goal is to enable the transparency of the AI-HW by designing self-explainable, trustworthy, reliable, and real-time verifiable AI hardware accelerators, capable of performing self-test, self-diagnosis, and self-correction.
More in details, the Ph.D. student will:
Analyze the possible failure mechanisms affecting the hardware;
From the knowledge of failure mechanisms, derive the corresponding hardware faults (i.e., the logical representation of a failure mechanism);
Analyze their impact on AI and XAI results , in terms of accuracy degradation and determine their criticality;
Design low-cost fault tolerance approaches to efficiently detect/correct HW faults, thus ensuring the correctness of the hardware, with the goal to ensure both correct AI and XAI decisions.
A possible approach to fault tolerance is to apply XAI techniques to produce explanations about the state of the hardware during inference and turn these explanations into actions to correct hardware faults. This Ph.D. subject targets the study of the impact of HW faults on both prototypes created by self-explainable models at training time and post-explanations at inference time. The starting point will be existing state-of-the-art AI HW accelerators optimized for energy efficiency and the outcome will be fault-tolerant versions, still energy efficient.
Candidate Requirements Good knowledge of computer architectures and embedded systems
Machine Learning (pytorch/tensorflow)
HW design: VHDL/Verilog basics, HW synthesis flow
Basic programming knowledge (C/C++, python)
Experience with High Level Synthesis (HLS) is a plus
Experience in fault tolerant architectures is a plus
Candidates must have a Master's degree (or equivalent) in Computer Science, Computer Engineering, or Electrical Engineering.
Languages: proficiency in written English and fluency in spoken English required.
Relational skills: The candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner.
Other valued appreciated: Open-mindedness, strong integration skills and team spirit.
Most importantly, we seek highly motivated candidates.
Languages:
FRENCH: Level Basic
ENGLISH: Level Good
Additional Information Partial reimbursement of public transport costs
Possibility of teleworking (90 days per year) and flexible organization of working hours
Partial payment of insurance costs
Monthly gross salary amounting to 2100 euros for the first and second years and 2200 euros for the third year.
Selection Process Please submit online: your resume, cover letter and letters of recommendation eventually.
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