Optical Systems Architect - Doctoral Student With The Dn Nestor (Portugal)

Detalhes da Vaga

Optical Systems Architect - Doctoral Student with the DN NESTOR (Portugal)
Research Engineer and Doctoral Student Infinera is looking for an excellent intern professional with a master's degree in electrical engineering, computer science, or physics to join our Optical Architecture Group in Lisbon, Portugal and enrol in a PhD program. The PhD work is part of the Doctoral Network (DN) NESTOR funded by the European Commission and it will be carried out at Infinera premises in Lisbon. As part of the training activities, the candidate will also have an extended secondment at Politecnico di Torino, Turin, Italy. The PhD degree will be awarded by Instituto Universitário de Lisboa (ISCTE).
The evolution of optical metro-aggregation networks will be paramount to sustain demanding applications such as 5G/6G, cloud services, and AI/ML. Importantly, not only will the capacity of these networks have to scale significantly, but that will need to be accomplished while key metrics such as cost, power consumption and footprint are kept as low as possible. On the transceiver side, pluggable and flexible coherent interfaces capable of slicing capacity in the optical domain to cope with asymmetric traffic patterns hold the promise of reducing CAPEX and OPEX and allow a native pay-as-you-grow deployment model. On the line system side, lowering CAPEX demands using a selective (i.e., optimized) deployment of pluggable and low-cost filtering/switching and amplification subsystems, that is, adopting a model where filters, switches, amplifiers are used only when needed to satisfy a given set of requirements. However, a customized line system solution may become sub-optimal as traffic increases, more transceivers are deployed, new ones become available or in case the network grows. This results in a multi-objective optimization problem, where (short-term) cost and performance, the latter impacting future cost, must be balanced according to specific priorities set by the network operator.
The research and development work will focus on modelling and optimizing next-generation metro-aggregation networks leveraging coherent pluggable transceivers. The main objectives include:
Assessment of appropriate line system architectures to cost-effectively support coherent pluggable transceivers capable of operating in point-to-point and point-to-multipoint modes.Implementation of fast and scalable optical performance models for short-/medium-reach transmission.Definition of multi-objective optimization problems targeting scalable and low-cost network deployment solutions and development of scalable optimization frameworks to solve them.Performance evaluation of the design algorithms developed. Assessment of cost, footprint and power-consumption metrics to compare the proposed architectures with state-of-the-art.Within the framework of this program, the candidate will work most of the time at the site of Infinera in Lisbon, where he/she will be part of a multi-disciplinary architecture team that actively contributes to the definition and implementation of Infinera's next-generation optical line system and planning tools.
Essential Functions / Key Responsibilities Investigate existing and new optical node architectures for metro-aggregation networks leveraging point-to-point and point-to-multipoint coherent pluggable transceivers.Develop multi-objective optimization algorithms to design metro-aggregation networks considering potentially conflicting objectives such as low upfront deployment cost and long-term scalability. Execute detailed techno-economic comparisons.Implement simplified models to estimate optical performance in metro-aggregation networks using coherent pluggable transceivers and the selected node architectures. These models will be used to ensure the feasibility of the solutions obtained.Work collaboratively with other forward-thinking team members and external researchers from academic and industry.Write and present internal and public reports and deliverables.Write and present technical papers in high-impact journals and conferences from the IEEE and OPTICA.Knowledge / Skills / Abilities: Understanding of digital communications and telecommunications systems.Knowledge of the most relevant subsystems of an optical communication system (i.e., transceivers, modulators, optical amplifiers, optical switches) and familiar with optical node architectures.Experience with optimization models and algorithms (e.g., integer linear programming models, heuristic algorithms).Knowledge of digital signal processing and optical transmission models.Excellent verbal and written communication skills. The candidate must be able to convey the results of the investigation work clearly and concisely in written form as well as in oral communications.Programming experience in Matlab, Python, Julia, or similar. The candidate must be able to develop his/her own simulation tools, or extend existing ones, to carry out the necessary analysis. Highly attentive to detail, motivated, and possessing troubleshooting skills.Education / Experience: Master's in electrical engineering/computer science/physicsB2-C1 English Level"This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as "Export-Controlled Information") controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No. 1 to Part 740, Title 15) to have an export control license to access our Export-Controlled Information, unless they meet certain exemptions provided under U.S. export control laws and regulations. The list of applicable countries in Country Group D:1, E:1 or E:2 may be updated by the U.S. government from time to time. The current processing time for an export control license is approximately 4 to 6 months. Your employment or engagement with Infinera shall be contingent on verifying your eligibility or requirement for obtaining a necessary license and/or authorization from the appropriate agency. You will be required to provide certain information for export control compliance assessment purposes, and your information will be reviewed by Infinera's hiring and export control teams to ensure compliance with the U.S. export control laws and regulations. Infinera will collect necessary documents (such as proof of citizenship etc.) to assess license/authorization requirements if you are offered and accept the position. Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment. About UsImagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.
If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!
To learn more about working at Infinera visit our main Career page.

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