DFT ENGINEER (HYBRID)
Portuguese Consultancy hires for hybrid work in Lisbon / Portugal. Only resumes will be accepted from those who already live in Portugal.
FLUENT PORTUGUESE AND ENGLISH (B2)
Please send only CV's in English.
Description:
We are hiring a Design Verification (DV) engineer. As a DFT engineer, you'll have the chance to make a significant impact on projects within the semiconductors industry.
Your responsibilities will include:
Implementing DFT in line with established test methodologies for advanced process nodes.
Conducting top and/or block-level DFT insertion, encompassing scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
Collaborating closely with the physical design team to address timing constraints/issues.
Verifying DFT circuitry and interfacing with other components/IPs to debug timing simulation issues.
Enhancing and debugging critical DfT KPIs, such as test coverage/pattern efficiency.
Conducting hierarchical retargeting.
Supporting silicon bring-up, diagnosis, and physical failure analysis.
We are looking for candidates with:
6+ years of hands-on experience in DFT and test flows using commercial EDA tools for large and complex SOCs.
Profound knowledge of DFT techniques, including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500 Std., and MBIST/LBIST.
Familiarity with leading EDA providers such as Synopsys DFT Compiler, Tetramax, VCS, Tessent, and Modus/Encounter tool suite.
Experience in RTL simulation, synthesis, linting, CDC and RDC checks, STA, DFT, and quality metrics is advantageous.
Proficiency in Perl/Tcl/Python scripting.
Excellent analytical and problem-solving abilities.
We value exceptional customer service and seek individuals who are naturally curious, thrive on challenging the status quo, and are committed to leaving things better than they found them. If this sounds like you, you'd be a valuable asset in this role. We welcome candidates at various levels of experience to apply.
Work Model: Hybrid.
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