In this role, you will be responsible for resource and project planning, coordination of geographically distributed analog layout teams, and for the quality assurance of layout implementations.
This role will involve close interaction and collaborative teamwork with multiple functional groups (front end, analog, ASIC, CAD) and the product teams globally. The ideal candidate will be an excellent communicator and comfortable managing multiple tasks.
You will be part of an advanced physical design team developing full custom analog and ASIC layout of high-speed integrated circuits. As an Analog & Mixed-Signal Layout Manager, you will be exposed to SerDes PHY design for PCIe, Ethernet, and other protocols. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Ideal background would include hands-on analog layout or ASIC physical design experience with project management background and aptitude.
Main Responsibilities:Assures high quality of Analog & Mixed-Signal Layout implementationsOwns cross team planning, collaboration, and coordination ensuring that geographically distributed teams are well-alignedMeasure project and performance using appropriate systems, tools and techniquesEstablish and maintain relationships with cross-functional teams, internal and external customersCreate and maintain comprehensive project documentationKey Qualifications:Deep understanding of physical design of analog and mixed signal CMOS circuitsExcellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customersSolid organizational skills including attention to detail and multi-tasking skillsAutonomous, timely decision maker and able to cope with interruptsExperience with advanced FinFET nodes, TSMC 16 nanometer and belowExperience with Design tool(s): Custom Compiler, Cadence Virtuoso or equivalentVerification tools: ICV, CalibreStrong working knowledge of MS Office Suite of applicationsPreferred Experience:MSEE or BSEE with a minimum of 8 years of related experienceExposure to SERDES design architectures, and layoutSolid understanding of digital / mixed signal flows and SOC integration challengesExperience in working with Jira/Atlassian (or other such) toolsAt Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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